dr.ing. D.M. Ziener (Daniel)

Daniel is currently an associate professor in the CAES group (Computer Architecture for Embedded Systems) at the faculty EEMCS of the University of Twente. From 2015 until 2017, he was a substitute professor for Cyber-Physical Systems at the Hamburg University of Technology, Germany. From 2010 to 2015, he had led the Reconfigurable Computing Group of the Chair of Hardware/Software Co-Design at Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany. His main research interests are the usage of partial dynamic reconfiguration of FPGAs, efficient usage of FPGA structures, design of signal processing FPGA cores, reliable and fault tolerant embedded systems, as well as security in FPGA-based systems. Daniel has (co-)authored more than 40 peer-reviewed publications, holds two patents, and serves as a program committee member of several international conferences (DATE, FPL, Reconfig, SPL) as well as a reviewer for several international journals.

Daniel took his university entrance qualification in 1998. He received his diploma degree (Dipl.-Ing. (FH)) in Electrical Engineering from University of Applied Science Aschaffenburg, Germany, in August 2002. Beside his studies, he gained industrial research experience during an internship at the IBM Germany Development Labs in Böblingen. From 2003 to 2009 he worked for the Fraunhofer Institute of Integrated Circuits (IIS) in Erlangen, Germany as a research staff in the electronic imaging department. Furthermore, in 2003 he joined the Chair of Hardware-Software-Co-Design at the University of Erlangen-Nuremberg, Germany, headed by Prof. Jürgen Teich as PhD student. In 2010 he received his PhD degree (Dr.-Ing.) and in 2017 his habilitation (Dr.-Ing. habil.).

Engineering & Materials Science

# Computer Hardware
# Field Programmable Gate Arrays (Fpga)
# Intellectual Property Core
# Particle Accelerators
# Query Processing
# Throughput
# Watermarking

Mathematics

# Field Programmable Gate Array

Research Interests

Partial dynamic reconfiguration of FPGAs
Efficient usage of FPGA structures
Design of signal processing FPGA cores
Reliable and fault tolerant embedded systems
Secure embedded systems
IP core watermarking

Irmak, H. , Ziener, D. , & Alachiotis, N. (2021). Increasing Flexibility of FPGA-based CNN Accelerators with Dynamic Partial Reconfiguration. In 2021 31st International Conference on Field-Programmable Logic and Applications (FPL) (pp. 306-311). [9556462] IEEE EDS. https://doi.org/10.1109/FPL53798.2021.00061

Asghar, A., Hettwer, B., Karimov, E. , & Ziener, D. (2021). Increasing Side-Channel Resistance by Netlist Randomization and FPGA-Based Reconfiguration. In S. Derrien, F. Hannig, P. C. Diniz, & D. Chillet (Eds.), Applied Reconfigurable Computing. Architectures, Tools, and Applications - 17th International Symposium, ARC 2021, Proceedings (pp. 173-187). (Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics); Vol. 12700 LNCS). Springer Science + Business Media. https://doi.org/10.1007/978-3-030-79025-7_12

Irmak, H., Corradi, F., Detterer, P. , Alachiotis, N. , & Ziener, D. (2021). A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs. Journal of Low Power Electronics and Applications, 11(3), [32]. https://doi.org/10.3390/jlpea11030032

Irmak, H. , Alachiotis, N. , & Ziener, D. (2021). An energy-efficient FPGA-based convolutional neural network implementation. In SIU 2021 - 29th IEEE Conference on Signal Processing and Communications Applications, Proceedings [9477823] IEEE. https://doi.org/10.1109/SIU53274.2021.9477823

de Vos, P., Kirchhoff, M. , & Ziener, D. (2020). A Complete Open Source Design Flow for Gowin FPGAs. In 2020 International Conference on Field-Programmable Technology (ICFPT) (Proceedings - 2020 International Conference on Field-Programmable Technology, ICFPT 2020; Vol. 2020). IEEE.

Asghar, S. M. A., Van Loo, R., Kruiper, T. , & Ziener, D. (2019). Optimizing FPGA-Based Streaming Applications for Throughput Using Pipelining. In Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019 (pp. 351-354). [8977878] (Proceedings - 2019 International Conference on Field-Programmable Technology, ICFPT 2019; Vol. 2019-December). IEEE. https://doi.org/10.1109/ICFPT47387.2019.00065

Blott, M., Liu, L. , Ziener, D., & Karras, K. (2019). Pipelined database processing circuit and method. (Patent No. 10482129). https://patents.justia.com/patent/10482129

Ziener, D. (2019). Security in Embedded Hardware. Universiteit Twente.

Ziener, D., Pirkl, J., & Teich, J. (2019). Configuration Tampering of BRAM-based AES Implementations on FPGAs. In 2018 International Conference on ReConFigurable Computing and FPGAs IEEE Computer Society. https://doi.org/10.1109/RECONFIG.2018.8641692

Posewsky, T. , & Ziener, D. (2018). Throughput optimizations for FPGA-based deep neural network inference. Microprocessors and microsystems, 60, 151-161. https://doi.org/10.1016/j.micpro.2018.04.004

Naar mijn profiel

Vakken in het huidig collegejaar worden toegevoegd op het moment dat zij definitief zijn in het Osiris systeem. Daarom kan het zijn dat de lijst nog niet compleet is voor het gehele collegejaar.