dr.ing. D.M. Ziener (Daniel)

Universitair hoofddocent

Over mij

Daniel is currently an associate professor in the CAES group (Computer Architecture for Embedded Systems) at the faculty EEMCS of the University of Twente. From 2015 until 2017, he was a substitute professor for Cyber-Physical Systems at the Hamburg University of Technology, Germany. From 2010 to 2015, he had led the Reconfigurable Computing Group of the Chair of Hardware/Software Co-Design at Friedrich-Alexander University Erlangen-Nürnberg (FAU), Germany. His main research interests are the usage of partial dynamic reconfiguration of FPGAs, efficient usage of FPGA structures, design of signal processing FPGA cores, reliable and fault tolerant embedded systems, as well as security in FPGA-based systems. Daniel has (co-)authored more than 40 peer-reviewed publications, holds two patents, and serves as a program committee member of several international conferences (DATE, FPL, Reconfig, SPL) as well as a reviewer for several international journals.

Daniel took his university entrance qualification in 1998. He received his diploma degree (Dipl.-Ing. (FH)) in Electrical Engineering from University of Applied Science Aschaffenburg, Germany, in August 2002. Beside his studies, he gained industrial research experience during an internship at the IBM Germany Development Labs in Böblingen. From 2003 to 2009 he worked for the Fraunhofer Institute of Integrated Circuits (IIS) in Erlangen, Germany as a research staff in the electronic imaging department. Furthermore, in 2003 he joined the Chair of Hardware-Software-Co-Design at the University of Erlangen-Nuremberg, Germany, headed by Prof. Jürgen Teich as PhD student. In 2010 he received his PhD degree (Dr.-Ing.) and in 2017 his habilitation (Dr.-Ing. habil.).


Field Programmable Gate Arrays (Fpga)
Neural Networks
Flow Control
Table Lookup


Research Interests
  • Partial dynamic reconfiguration of FPGAs
  • Efficient usage of FPGA structures
  • Design of signal processing FPGA cores
  • Reliable and fault tolerant embedded systems
  • Secure embedded systems
  • IP core watermarking


Posewsky, T., & Ziener, D. (2018). Throughput optimizations for FPGA-based deep neural network inference. Microprocessors and microsystems, 60, 151-161. DOI: 10.1016/j.micpro.2018.04.004
Posewsky, T., & Ziener, D. (2018). A Flexible FPGA-based Inference Architecture for Pruned Deep Neural Networks. In M. Berekovic, R. Buchty, H. Hamann, D. Koch, & T. Pionteck (Eds.), Architecture of Computing Systems – ARCS 2018: 31st International Conference, Braunschweig, Germany, April 9–12, 2018, Proceedings (pp. 311-323). (Lecture notes in computer science; Vol. 10793). Braunschweig, Germany: Springer. DOI: 10.1007/978-3-319-77610-1_23
Schmidt, B., Ziener, D., Teich, J., & Zöllner, C. (2017). Optimizing scrubbing by netlist analysis for FPGA configuration bit classification and floorplanning. Integration, the VLSI Journal, 59, 98-108. DOI: 10.1016/j.vlsi.2017.06.012
Echavarria, J., Wildermann, S., Becher, A., Teich, J., & Ziener, D. (2017). FAU: Fast and error-optimized approximate adder units on LUT-Based FPGAs. In 2016 International Conference on Field-Programmable Technology, FPT 2016 (pp. 213-216). [7929536] IEEE. DOI: 10.1109/FPT.2016.7929536
Koch, D., Ziener, D., & Hannig, F. (2016). FPGA versus software programming: Why, when, and how? In D. Koch, F. Hannig, & D. Ziener (Eds.), FPGAs for Software Programmers (pp. 1-21). Springer International Publishing Switzerland. DOI: 10.1007/978-3-319-26408-0_1
Posewsky, T., & Ziener, D. (2016). Efficient deep neural network acceleration through FPGA-based batch processing. In 2016 International Conference on Reconfigurable Computing and FPGAs, ReConFig 2016 [7857167] Institute of Electrical and Electronics Engineers Inc.. DOI: 10.1109/ReConFig.2016.7857167
Ziener, D., Bauer, F., Becher, A., Dennl, C., Meyer-Wegener, K., Schurfeld, U., ... Weber, H. (2016). FPGA-based dynamically reconfigurable SQL query processing. ACM Transactions on Reconfigurable Technology and Systems, 9(4), [25]. DOI: 10.1145/2845087
Becher, A., Echavarria, J., Ziener, D., Wildermann, S., & Teich, J. (2016). A LUT-Based Approximate Adder. In 24th IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM) (pp. 27). [7544739] Piscataway, NJ: IEEE. DOI: 10.1109/FCCM.2016.16
Becher, A., Ziener, D., Meyer-Wegener, K., & Teich, J. (2016). A co-design approach for accelerated SQL query processing via FPGA-based data filtering. In 2015 International Conference on Field Programmable Technology, FPT 2015 (pp. 192-195). [7393148] IEEE. DOI: 10.1109/FPT.2015.7393148

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Universiteit Twente
Faculteit Elektrotechniek, Wiskunde en Informatica
Zilverling (gebouwnr. 11), kamer 5035
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Universiteit Twente
Faculteit Elektrotechniek, Wiskunde en Informatica
Zilverling  5035
Postbus 217
7500 AE Enschede