University of Twente
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dr.ir. M. Ottavi (Marco)

Universitair hoofddocent

Over mij

Marco Ottavi heeft elektrotechniek gestudeerd aan de Universiteit van Rome "La Sapienza", en een doctoraat behaald in telecommunicatie- en micro-elektronica-engineering aan de Universiteit van Rome "Tor Vergata". Van 2003 tot 2007 was hij bezoekend onderzoeker en onderzoeksassistent aan de Northeastern University in Boston (VS). In 2006 was hij bezoekend onderzoeker aan Sandia National Laboratories in Albuquerque (VS). In 2007 kreeg hij een permanent verblijf in de Verenigde Staten ("green card") met de EB1-visum voor "uitmuntende onderzoekers". Van 2007 tot 2009 was hij senior ontwerp-ingenieur bij Advanced Micro Devices (AMD) in Boxborough (VS). In 2009 trad hij toe tot de Universiteit van Rome "Tor Vergata" als winnaar van een "Rientro dei Cervelli" beurs; sinds 2014 is hij associate professor aan dezelfde universiteit. In 2021 trad hij toe tot de groep Computer Architecture for Embedded Systems (CAES) als associate professor.

Expertises

Engineering & Materials Science
# Cellular Automata
# Data Storage Equipment
# Electric Power Utilization
# Error Correction
# Memristors
# Networks (Circuits)
# Reduced Instruction Set Computing
# Switches

Verbonden aan

Onderzoek

Mijn onderzoek richt zich op betrouwbare computing systemen op basis van opkomende technologieën en paradigma's. Op deze onderwerpen heb ik meer dan 150 bijdragen gepubliceerd op internationale congressen en tijdschriften waarvan ik ook reviewer en organisator ben. Van 2011 tot 2015 heb ik het Europese project COST IC1103 MEDIAN (Manufacturable and Dependable Multicore Architectures at Nanoscale) geleid. Ik ben en ben geweest Associate Editor voor IEEE Transactions on Emerging Topics in Computing, IEEE Transactions on Nanotechnology en IEEE Nanotechnology Magazine. Ik ben een senior lid van IEEE.

Publicaties

Recent
Uchoa, H., Arora, V., Vermoen, D. , Ottavi, M. , & Alachiotis, N. (2023). Exploring Genomic Sequence Alignment for Improving Side-Channel Analysis. In G. Tsudik, M. Conti, K. Liang, & G. Smaragdakis (Eds.), Computer Security – ESORICS 2023: 28th European Symposium on Research in Computer Security, The Hague, The Netherlands, September 25–29, 2023, Proceedings, Part III (pp. 203-221). (Lecture Notes in Computer Science; Vol. 14346). Springer. https://doi.org/10.1007/978-3-031-51479-1
Palumbo, A. , Ottavi, M., & Cassano, L. (2023). Built-in Software Obfuscation for Protecting Microprocessors against Hardware Trojan Horses. In L. Cassano, M. Psarakis, M. Traiola, & A. Bosio (Eds.), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 36). IEEE. https://doi.org/10.1109/DFT59622.2023.10313534
Böhmer, K., Forlin, B., Cazzaniga, C., Rech, P., Furano, G. , Alachiotis, N. , & Ottavi, M. (2023). Neutron Radiation Tests of the NEORV32 RISC-V SoC on Flash-Based FPGAs. In L. Cassano, M. Psarakis, M. Traiola, & A. Bosio (Eds.), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 36). IEEE. https://doi.org/10.1109/DFT59622.2023.10313556
Palumbo, A., Cassano, L., Reviriego, P. , & Ottavi, M. (2023). Improving the Detection of Hardware Trojan Horses in Microprocessors via Hamming Codes. In L. Cassano, M. Psarakis, M. Traiola, & A. Bosio (Eds.), 36th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2023 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 36). IEEE. https://doi.org/10.1109/DFT59622.2023.10313563
Nikiema, P. R., Palumbo, A., Aasma, A., Cassano, L., Kritikakou, A., Kulmala, A., Lukkarila, J. , Ottavi, M., Psiakis, R., & Traiola, M. (2023). Towards Dependable RISC-V Cores for Edge Computing Devices. In A. Savino, M. Maniatakos, S. di Carlo, & D. Gizopoulos (Eds.), 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design (IOLTS) (Proceedings - 2023 IEEE 29th International Symposium on On-Line Testing and Robust System Design, IOLTS 2023). IEEE. https://doi.org/10.1109/IOLTS59296.2023.10224862
Bolat, A., Tugrul, Y. C., Celik, S. H., Sezer, S. , Ottavi, M., & Ergin, O. (2023). DEV-PIM: Dynamic Execution Validation with Processing-in-Memory. In Proceedings - 2023 IEEE European Test Symposium, ETS 2023 (Proceedings of the European Test Workshop; Vol. 2023-May). IEEE. https://doi.org/10.1109/ETS56758.2023.10174063
Forlin, B. E., van Huffelen, W., Cazzaniga, C., Rech, P. , Alachiotis, N. , & Ottavi, M. (2023). An unprotected RISC-V Soft-core processor on an SRAM FPGA: Is it as bad as it sounds? In Proceedings - 2023 IEEE European Test Symposium, ETS 2023 (Proceedings IEEE European Test Symposium (ETS); Vol. 2023). IEEE. https://doi.org/10.1109/ETS56758.2023.10174076
Ebrahimi, H. (2023). Design and verification of embedded instruments for detecting intermittent resistive faults in electronic systems. [PhD Thesis - Research UT, graduation UT, University of Twente]. University of Twente. https://doi.org/10.3990/1.9789036557603
Barbirotta, M., Cheikh, A., Mastrandrea, A., Menichelli, F. , Ottavi, M., & Olivieri, M. (2023). Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core. Journal of Low Power Electronics and Applications, 13(1). https://doi.org/10.3390/jlpea13010002
Annink, E. B., Rauwerda, G., Hakkennes, E., Menicucci, A., Mascio, S. D., Furano, G. , & Ottavi, M. (2022). Preventing Soft Errors and Hardware Trojans in RISC-V Cores. In L. Cassano, S. Chakravarty, & A. Bosio (Eds.), Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2022-October). IEEE. https://doi.org/10.1109/DFT56152.2022.9962340
Cassano, L., Mascio, S. D., Palumbo, A., Menicucci, A., Furano, G., Bianchi, G. , & Ottavi, M. (2022). Is RISC-V ready for Space? A Security Perspective. In L. Cassano, S. Chakravarty, & A. Bosio (Eds.), Proceedings - 35th IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2022 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2022-October). IEEE. https://doi.org/10.1109/DFT56152.2022.9962352
Bala, A., Khandelwal, S., Jabir, A. , & Ottavi, M. (2022). Yield Evaluation of Faulty Memristive Crossbar Array-based Neural Networks with Repairability. In A. Savino, P. Rech, S. Di Carlo, & D. Gizopoulos (Eds.), 2022 IEEE 28th International Symposium on On-Line Testing and Robust System Design (IOLTS) IEEE. https://doi.org/10.1109/IOLTS56730.2022.9897183
Coluccio, A., Ieva, A., Riente, F., Roch, M. R. , Ottavi, M., & Vacca, M. (2022). RISC-Vlim, a RISC-V Framework for Logic-in-Memory Architectures. Electronics, 11(19), Article 2990. https://doi.org/10.3390/electronics11192990
Khandelwal, S. , Ottavi, M., Martinelli, E., & Jabir, A. (2022). Low power memristive gas sensor architectures with improved sensing accuracy. Journal of Computational Electronics, 21(4), 1005-1016. https://doi.org/10.1007/s10825-022-01890-0
Bolat, A., Celik, S. H., Olgun, A., Ergin, O. , & Ottavi, M. (2022). ERIC: An Efficient and Practical Software Obfuscation Framework. In Proceedings - 52nd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2022 (pp. 466-474). (Proceedings - Annual IEEE/IFIP International Conference on Dependable Systems and Networks, DSN 2022; Vol. 2022). IEEE. https://doi.org/10.1109/DSN53405.2022.00053
Arikan, K., Palumbo, A., Cassano, L., Reviriego, P., Pontarelli, S., Bianchi, G., Ergin, O. , & Ottavi, M. (2022). Processor Security: Detecting Microarchitectural Attacks via Count-Min Sketches. IEEE transactions on very large scale integration (VLSI) systems, 30(7), 938-951. https://doi.org/10.1109/TVLSI.2022.3171810
Palumbo, A., Cassano, L., Luzzi, B., Hernández, J. A., Reviriego, P., Bianchi, G. , & Ottavi, M. (2022). Is your FPGA bitstream Hardware Trojan-free? Machine learning can provide an answer. Journal of systems architecture, 128, Article 102543. https://doi.org/10.1016/j.sysarc.2022.102543
De Rossi, F., Taheri, B., Bonomo, M., Gupta, V., Renno, G., Yaghoobi Nia, N., Rech, P., Frost, C., Cazzaniga, C., Quagliotto, P., Di Carlo, A., Barolo, C. , Ottavi, M., & Brunetti, F. (2022). Neutron irradiated perovskite films and solar cells on PET substrates. Nano Energy, 93, Article 106879. https://doi.org/10.1016/j.nanoen.2021.106879
Gupta, V., Panunzi, G., Khandelwal, S., Martinelli, E., Jabir, A. , & Ottavi, M. (2021). Reliability Assessment of Memristor based Gas Sensor Array. In L. Dilillo, L. Cassano, & A. Papadimitriou (Eds.), 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (pp. 1-6). Article 9568304 (IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT); Vol. 2021). IEEE. https://doi.org/10.1109/DFT52944.2021.9568304
Palumbo, A., Cassano, L., Reviriego, P., Bianchi, G. , & Ottavi, M. (2021). A Lightweight Security Checking Module to Protect Microprocessors against Hardware Trojan Horses. In L. Dilillo, L. Cassano, & A. Papadimitriou (Eds.), 2021 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT) (pp. 1-6). Article 9568291 (Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT; Vol. 2021-October). IEEE. https://doi.org/10.1109/DFT52944.2021.9568291
Chattopadhyay, S., Santikellur, P., Chakraborty, R. S., Mathew, J. , & Ottavi, M. (2021). A Conditionally Chaotic Physically Unclonable Function Design Framework with High Reliability. ACM transactions on design automation of electronic systems, 26(6), Article 3460004. https://doi.org/10.1145/3460004
Gnoli, L., Riente, F. , Ottavi, M., & Vacca, M. (2021). A memristor-based sensing and repair system for photovoltaic modules. Microelectronics reliability, 117, Article 114026. https://doi.org/10.1016/j.microrel.2020.114026

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Bezoekadres

Universiteit Twente
Faculty of Electrical Engineering, Mathematics and Computer Science
Zilverling (gebouwnr. 11), kamer 5039
Hallenweg 19
7522NH  Enschede

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Postadres

Universiteit Twente
Faculty of Electrical Engineering, Mathematics and Computer Science
Zilverling  5039
Postbus 217
7500 AE Enschede

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